Call for Participation

[pdf version is here](As of 2019-Feb-5)

Keynote Presentations

“GPU: A true AI Cool-Chip with High Performance/Power Efficiency and Full-Programmability”

Toru Baji   (NVIDIA)

Abstract:  Low-power design is a standard practice these days, so quite often people do not pay much attention on the details. This may create misconception and misunderstanding. An example is a simple statement “Our design consumes 100mW”. Power consumption cannot be declared as a single concrete number because of complications in the estimation or measurement process with inherent inaccuracies and uncertainties. Another popular example is “Our design consumes lowest power of 100mW”. After understanding that a chip is typically designed with huge amount of margins, it is easy to see that the limit is far beyond. A few of these details of low power design, which often go unnoticed but deserve careful consideration, are addressed in this talk.


Toru Baji graduated from Osaka University Graduate School and joined Hitachi’s Central Research Lab in 1977. There he conducted research in solid-state image sensors and processor architecture.   From 1984, he was engaged in analog-digital circuit and processor architecture research at University of California, Berkeley and Hitachi America R&D respectively. After transferred to Hitachi’s Semiconductor Division in 1993, the Division has been moved to Renesas and he served as a General Manager of Automotive Application Technology Department.   He joined NVIDIA in 2008 as a Senior Solution Architect for automotive business, supporting worldwide customers for automotive processors applications. Since 2016, he serves as an NVIDIA technology advisor and GPU Evangelist.

 

“Quantum Computing at IBM – from hardware to software (Tentative)”

Patryk Gumann   (IBM)

Abstract:  TBA.

Patryk Gumann received his PhD in experimental physics from Darmstadt University of Technology in Germany, in 2007. He has worked at various research facilities over his career, including Leiden University, The Netherlands, the Institute for Solid State Physics at the University of Tokyo, the Low Temperature Laboratory at Kyoto University, Rutgers University, The Institute for Quantum Computing at the University of Waterloo in Canada, and the Department of Physics at Harvard University. His research focus has ranged from quantum fluids and solids, quantum sensing, including nitrogen vacancy defects in diamonds, and phosphorus defects in silicon, to experimental superconducting quantum comping – which he has been pursuing at IBM since 2016, where he is a manager for quantum processor & system integration group.

 

“Architectures for efficient, low-power AI Edge processing”

Sanjay Patel   (Wave Computing)

Abstract:  There is a need in AI to move intelligence to the edge to circumvent challenges that include latency, security, and bandwidth for AI use cases at the edge. This trend will accelerate with the continued proliferation of IoT.  Utilization of cloud-base, AI-as-a-service to address edge use cases can become exceedingly expensive. AI processing on a remote server system can be unreliable where connectivity is poor.   Processing AI at the edge comes with its own challenges, achieving desired performance at low-power with constrained memory and processing resources. This talk discusses the ramifications of moving AI processing to the edge, focusing on the potential of CPU-centric edge-AI Architectures.

Sanjay Patel is a Director of IP Architecture at Wave Computing. He has worked at Motorola, Sun Microsystem, Afara Websystems, Oracle, MIPS Technologies in the past. He has focused on processor and SOC design in the context of multi-threaded and multi-core system architectures. His interests now include the development of low-power compute solutions for neural networks for edge AI processing platforms. He is the owner of approximately 20 patents in the area of compute architectures.

 

“Vector Engine Processor of NEC’s Brand-New Supercomputer SX-Aurora TSUBASA”

Yoshihiro Konno   (NEC)

Abstract:  TBA.

Bio:  TBA.

 

 

Invited presentations

“DLU and Domain Specific Computing”

Takumi Maruyama  (Fujitsu)

Abstract:  TBA

 

Takumi Maruyama is a senior director of AI Platform Business Unit at Fujitsu, and an architect of DLU, which is the first AI processor Fujitsu ever designed. He started working on the first SPARC64 processor design in 1993, and has been involved in the development of various SPARC64 processors, including SPARC64 VIIIfx which was a processor of K supercomputer. He holds a BE in Mathematical Engineering and Instrumentation Physics from the University of Tokyo.

 

 

“A64FX High Performance Processor Architecture and its Design Challenges”

Shuji Yamamura  (Fujitsu)

Abstract:  TBA

Bio: TAB

 

 

Panel Discussion

Topics: “Where will the computer architecture go?”

Organizer and Moderator:
Yasunori Kimura (JST)
Panelist:
            TBA

 

Abstract:  Discussions on Computer Architecture are on the rise. Domain Specific Architecture, Deep Learning chips, Approximate Computing, Security Aware Architecture, and even Quantum Computers are some of these.   Along with this, users’ requests are also changing and various; some expect that ICT or A.I. support and help us to solve social problems and lead an enjoyable life. In addition, demands from the technology side such as low power consumption capability are also critical.  Taking these technology and social changes around us into account, at this panel discussion, we would discuss what we architects and engineers should do right now, how we should act to promote R&D in a long term perspective, to meet the needs and expectations of society eventually. We would also like to discuss human resource development, and project management system.


Yasunori Kimura is now Senior Fellow at Fujitsu Laboratories Ltd. and Principal Fellow at Japan Science and Technology Agency (JST).
He joined Fujitsu Limited in 1981. Since then throughout his career, he has been engaged primarily in computer system design and development at the company.  To name a few, he had contributed to the Japanese fifth generation computer systems project, and led the ‘KEI’ supercomputer development team there.
He had been President and CEO of Fujitsu Laboratories of America, Inc. in California from 2011 through 2015.   He holds the positions of the organizations above since January, 2017.  He spent a summer at Stanford University as a visiting scholar in 1995, and served as Visiting Professor at the University of Tokyo for four years from 2002 where he earned a Ph.D. in Computer Science.

 

Special Sessions (invited lectures)

“Design, Compilation, and Acceleration for Deep Neural Networks in IoT Applications”

Deming Chen (UIUC)

Abstract:  Many new IoT (Internet of Things) applications are driven by the fast creation, adaptation, and enhancement of various types of Deep Neural Networks (DNNs). DNNs are computation intensive. Without efficient hardware implementations of DNNs, these promising IoT applications will not be practically realizable. In this talk, we will analyze several challenges facing the AI and IoT community for mapping DNNs to hardware accelerators. Especially, we will evaluate FPGA’s potential role for accelerating DNNs for both the cloud and edge devices. Although FPGAs can provide desirable customized hardware solutions, they are difficult to program and optimize. We will present a series of effective design techniques for implementing DNNs on FPGAs with high performance and energy efficiency. These include automated hardware/software co-design, the use of configurable DNN IPs, resource allocation across DNN layers, smart pipeline scheduling, Winograd and FFT techniques, and DNN reduction and re-training. We showcase several design solutions including Long-term Recurrent Convolution Network (LRCN) for video captioning, bidirectional LSTM for machine translation, and Inception module (GoogleNet) for face recognition. We will also present some of our recent work on developing new DNN models and data structures for achieving higher accuracy for several interesting applications such as crowd counting, music synthesis, and smart sound.

Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He joined the ECE department of University of Illinois at Urbana-Champaign (UIUC) in 2005 and has been a full professor in the same department since 2015. His current research interests include machine learning and acceleration, GPU and reconfigurable computing, system-level and high-level synthesis, computational genomics, and hardware security. He has given about 100 invited talks sharing these research results worldwide. Dr. Chen is a technical committee member for a series of top conferences and symposia on EDA, FPGA, low-power design, and embedded systems design. He is an associated editor for several leading IEEE and ACM journals. He received the NSF CAREER Award in 2008, the ACM SIGDA Outstanding New Faculty Award in 2010, and IBM Faculty Award in 2014 and 2015. He also received eight Best Paper Awards and the First Place Winner Award of DAC International Hardware Contest on IoT in 2017. He is included in the List of Teachers Ranked as Excellent in 2008 and 2017. He was involved in two startup companies previously, which were both acquired. In 2016, he co-founded a new startup, Inspirit IoT, Inc., for design and synthesis for machine learning applications targeting the IoT industry. He is the Donald Biggar Willett Faculty Scholar, an IEEE Fellow, an ACM Distinguished Speaker, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems.

 

“Low Power Design: Facts, Myths, and Misunderstandings”

Youngsoo Shin  (KAIST)

Abstract:  Low-power design is a standard practice these days, so quite often people do not pay much attention on the details. This may create misconception and misunderstanding. An example is a simple statement “Our design consumes 100mW”. Power consumption cannot be declared as a single concrete number because of complications in the estimation or measurement process with inherent inaccuracies and uncertainties. Another popular example is “Our design consumes lowest power of 100mW”. After understanding that a chip is typically designed with huge amount of margins, it is easy to see that the limit is far beyond. A few of these details of low power design, which often go unnoticed but deserve careful consideration, are addressed in this talk.


Youngsoo Shin received the B.S., M.S., and Ph.D. degrees in electronics engineering from Seoul National University, Korea. From 2001 to 2004, he was a Research Staff Member with IBM T. J. Watson Research Center, Yorktown Heights, NY, USA. He joined the School of Electrical Engineering, KAIST, Korea, in 2004, where he is currently a Professor. His recent research interests include low-power design, computational lithography, design for manufacturability, and neuromorphic circuit design. Since 2016, Dr. Shin has been a CTO of Baum, which specializes in fast power analysis solution. He is an IEEE Fellow.