COOL Chips II
Kyoto Research Park,JAPAN
April 26 - 27, 1999
Wednesday, April 26
Plenary Session 1
Opeing Remarks
Tadao Nakamura(COOL Chips Ⅱ Organizing Committee)
Akira Kubata(The Ministry of International Trade and Industry)
Makoto Nagao(IEICE)
Keynote Speech
Basic Issues in Processor Architecture in the Era of Deep Submicron Technology
Michael Flynn(Stanford Univ.)
Invited Speech 1
In-System Design Verification of Processors
C-M Kyung(KAIST)
Invited Speech 2
Evolutionary Systems for Brain Communications
Shimohara(ATR)
Session 1 : Accelerators
A 0.25 um CMOS, 5.1 M-Transistor, Dynamically Reconfigurable Logic Engine(DRLE)
Taro Fujii et.al. (NEC)
A Cryptgraphic Accelerator Card with Small Fast Low-Power RSA Engines
Kohji Takano et.al. (IBM Research)
A High-Performance Public Key Cryptgraphy Co-Processor for Super Multi-Purpose Smart Card
Hiroki Sutoh(NTT)
Poster Session
P1 "A Cost-Effective Branch Target Buffer with a Two-Level Table Organization"
Ryotaro Kobayashi et.al. (Nagoya Univ.)
P2 "A Single-Chip Voice over Internet Protocol LSI"
Masazumi Isaka (OKI Electric)
P3 "A Low Power Design Methodology for Large-Scale ASICs"
Yoshinao Kobayashi (IBM)
P4 "An Efficient Coprocessor Interface Scheme in CalmRISC"
Hong-Kyu Kim et.al. (Samsung Semiconductor)
P5 "An Effecient Implementation of BIST based on IEEE 1149.1 for Fixed Point DSP Processor"
Sun-Woong Yang et.al.(Soongsil Univ.)
P6 "Implementation of the Global Embedded Processor Debug Interface Standard for the MCORE Architecture"
Rich Collins (Motorola)
P7 Cancelled
P8 "Design of Self-Testable Dual-Port Embedded Memory"
Nam-Kyu Jung et.al.(Soongsil Univ.)
P9 "A Design of Low Power 16-bit ALU"
Beom Seon Ryum et.al. (Chungbuk National Univ.)
P10 "A Processor Architecture and Evaluation which Correspond to the Deviation of the Memory Latency"
Daisuke Mitake(Tokai Univ.)
P11 "ARM920T Low-Power High-Performance System-On-A-Chip Processor"
Guy Larri (ARM)
Session 2 : Multimedia and Graphics
Instruction Decode and Clock Skew Control for a 2.3V, 300MHz Multimedia Processor
Hidehiro Takata et.al. (Mitsubishi Electric)
SuperENC: MPEG-2 Video Encoder LSI based on Three-Layer Copoperative Architecture
Mitsuo Ikeda (NTT)
VLIW Geometry Processor for 3D Graphics Acceleration
Sang-Joon Nam (KAIST)
Thursday, April 27
Plenary Session 2
Invited Speech 3
Low Power and High Speed Digital Signal Processor
Hiroshi Takahashi (TI Japan)
Invited Speech 4
Technology Scaling and Design Challenges
Shekhar Borkar(Intel)
Session 3 : Link and Switch
Responsive Processor for Parallel/Distributed Real-Time Processing
Nobuyuki Yamazaki et.al (ETL)
MBP-light: A Processor for Management of The Distributed Shared Memory on JUMP-1
Hiroaki Inoue et.al. (Keio Univ. and Univ. of Tokyo)
A 10-Gb/s 4x2 CMOS/SIMOX Switch LSI for a 640-Gb/s ATM Switching System
Yusuke Ohtomo et.al. (NTT)
Invited Speech 5
VLIW Processors: Efficiently Exploiting Instruction-level Parallelism Kevin W.Rudd (Stanford Univ.)
Session 4: High-Performance Embedded RISC
An Efficient High-Performance RISC Microprocessor Family
Anna Chiang (SandCraft Inc.)
Superscalar Embedded Processor with SDRAM Interface
Hiroyuki Fujiyama et.al. (Fujitsu)
Session 5: Signal Processing Centric Architecture
A High-Performance ISDN Processor
Hirokazu Tagiri (ROHM)
Embedded Micro-RISC Architecture Addresses Low Power Wireless Market Requirements
David R.Gonzales (Motorola)
SH-3 DSP Microprocessor
Cang-HSA Tran (Hitachi Semicond. America)
Closing Remarks