COOL Chips V
April 18 - 20, 2002
Kikai-Shinko-Kaikan, Tokyo, JAPAN
April 18, 2002
Session I : Plenary Session
Co-Chairs: Shuhei Iwade (Mitsubishi Electric), Takeshi Ogura (NTT)
Welcome and Opening Remarks
Tadao Nakamura
Satoshi Iwata
Hiromasa Itoh
Allen J. Baum
Keynote Presentation 1
Electronic Numbering of Products and Documents Using the μ-Chip, a Micro-rfID(radio-frequency IDentification) Backed by Networked Database, Brings About New Business and Life Styles, Innovating Manufacturing, Distribution, Consumption, Tracking, and Recycling.
Shojiro Asai (Senior Corporate Officer, Hitachi Ltd.)
Session II :Keynote Presentation 2
Chair: Hirohisa Gambe (Fujitsu Labs.)
Where Is the Next Silicon Valley for Chip and Related Industries?Richard Dasher (Stanford Univ.)
Session III : Invited Presentation 1
Chair:Naoki Nishi (NEC)
Wireless Convergence Calls for Advanced Systems Level Designs
Nigel C. Dixon (TI Japan)
Session IV : Communication Systems
Chair: Atsushi Takahara(NTT)
Deskew-LSI for 10-Gbit/s parallel optical links in RHiNET-3 system
Hiroaki Nishi, Junji Yamamoto, Kozo Ohsugi, Katsuyoshi Harasawa and Shinji Nishimura (RWCP, Hitachi Information Technology, Hitachi)
Multi-Port Gigabit Network Processor and Scalable Switch Fabric
You-Sung Chang, Ju-Hwan Yi, Hun-Seung Oh, Jung-Bum Chun, Moo-Kyung Kang, Seung-Wang Lee, Jun-Hee Lee, Hee-Jae Jung, Sang-Ho Kim, Jin-Suc Kim, Sang-Heon Lee, Yong-Hwan Kim, Yu-Sik Lee, Young-Jun Ahn, and Chong-Min Kyung (PAION Co., Ltd./KAIST)
Session V : Video and Graphics chips
Chair: Makoto Ikeda (Univ. of Tokyo)
A Low Power MPEG-4 Codec LSI for Mobile Video Application
Li Jiang, Peilin Liu, Hiroshi Nakayama, Toshiyuki Yoshitake, Hiroshi Komazaki, Yasuhiro Watanabe, Hisakatsu Araki, Kiyonori Morioka, Shinhaeng Lee, Hajime Kubosawa and Yukio Otobe (Fujitsu Laboratories Ltd)
Low Power MPEG-4 Video Codec Hardware for Portable Applications
Chi-Weon Yoon and Hoi-Jun Yoo (KAIST)
High performance video processor with full motion reverse playback function using novel algorithm for next generation MPEG2 application
Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Yuh Matsuda, Tsugio Mori, Shin'ichiro Okada, Tsuyoshi Watanabe, Yasoo Harada, Morio Matsudaira and Yoshifumi Matsushita (SANYO Electric Co., Ltd.)
Application Processor for 3G Cellular Phones
Takanobu Tsunoda, Tetsuya Yamada, Yuuki Kondoh, Kenji Kitagawa, Ken Tatezawa, Takuichiro Nakazawa, Takahiro Irita, Saneaki Tamaki, Tetsuya Kamei, Makoto Ishikawa, Koji Yamada, Norimasa Otsuki, Naohiko Irie, Fumio Arakawa, Motoaki Satoyama, Toshihiro Hattori, Ikuya Kawasaki and Kunio Uchiyama (Hitachi, Super-H Japan)
Session VI : Panel Discussion
Chair and Organizer: Taisuke Boku (Univ. of Tsukuba)
Do Game chips contribute to High Performance Computing ?
Panelists:
Nobuyuki Yamasaki (Keio University/AIST),
Hiroshi Nakamura (Univ. of Tokyo),
Ryutaro Himeno (Riken),
David Kirk (nVIDIA)
April 19, 2002
Session VII : Invited Presentations
Co-Chairs: Gensuke Goto(Yamagata Univ.),Seiji Yamaguchi (Matsushita)
Invited Presentation 2
GRAPE Project--Future of High-performance Scientific Computing ?
Junichiro Makino(Univ. of Tokyo)
Invited Presentation 3
Challenge of System-in-a-package and MEMS Technology
Min-Shyong Lin and Chengkuo Lee (Asia Pacific Microsystems, Inc.)
Session VIII : Poster Short Speeches
Chair: Hideharu Amano (Keio Univ.)
Poster 1: Implementation of the Reconfigurable Processor with ability of Every-Cycle Reconfiguration and Execution
Kazuya Tanigawa, Tomohiro Inoue, Tetsuo Hironaka, Noriyoshi Yoshida (Hiroshima City Univ.)
Poster 2: A Simple Asynchronous Switch
Ken-ichiro Ishikawa, Hideharu Amano (Keio Univ.)
Poster 3: Seminconductor IP Accelerator Core for Ultra Low Power MPEG-4 Video Decode in Systems-on-Silicon
J.Dunlop, A.Simpson, S.Masud, M.Wylie, J.Cochrane, R.Kinkead (Amphion Smiconductor Ltd.)
Poster 4: An IPsec ESP gateway on the "Comet NP" encryption network processor chip
Masanori Naganuma, Akira Jinzaki (Fujitsu Lab. Ltd.)
Poster 5: Design and Implementation of LUTs for Plastic Cell Architecture
Jun'ichiro Takemoto, Toshihiro Goto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki University)
Poster 6: Implementation of a Finite Impulse Response Filter on Plastic Cell Architecture
Takeshi Kozasa, Akira Kawano, Nobuyoshi Murakami, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki University)
Session IX : Innovative Architectures
Chair: Fumio Arakawa (Super-H Japan)
Cascade ALU Architecture: Preserving Performance Scalability with Power Consumption Suppressed
Motokazu Ozawa, Hiroshi Nakamura and Takashi Nanya (RCAST, Univ. Tokyo)
Three-Dimensional Processor System Fabricated by Wafer Stacking Technology
Taizo Ono, Tomokatsu Mizukusa, Tomonori Nakamura, Yusuke Yamada, Yuji Igarashi, Tetsu Morooka, Hiroyuki Kurino and Mitsumasa Koyanagi (Tohoku Univ.)
Pipeline Stage Unification for Low-Power Consumption
Hajime Shimada, Hideki Ando and Toshio Shimada (Nagoya Univ.)
An Evaluation of Different Branch Predictors for Low-Power Embedded Processor
Dongrui Fan, Hongbo Yang, Guang R. Gao and Rongcai Zhao ( Chinese Academy of Sciences, Beijing and Univ. of Delaware)
Session X: Audio Chips
Chair: Kazuo Taki (AIL Co., Ltd./ Kobe Univ.)
CPAD4: A Highly Integrated Low Power Digital Audio Chip
Sangyeun Cho, Seungjae Chung, Sanghyun Park, Sangwoo Kim, Sungjin Jung, Wooyoung Jung, Sanghoon Moon and Yongchun Kim (Samsung Electronics Co.)
Low power consumption audio digital processor with 1Mbit SRAM
Yoshihisa Arai (TOSHIBA Corporation Semiconductor Company)
New Cost-effective VLSI Implementation of Synthesis Subband for MP3 Audio Decoder
Tsung-Han Tsai (EE, National Central University, Taiwan)
Session XI: Processors I
Chair: Kenji Kise(UEC)
A 400 MHz RISC Microprocessor
Akira Yamada, Yasuhiro Nunomura, Hiroaki Suzuki, Hisakazu Sato, Niichi Itoh, Tetsuya Kagemoto, Hironobu Ito, Takashi Kurafuji, Nobuharu Yoshioka, Jingo Nakanishi, Hiromi Notani, Rei Akiyama, Atsushi Iwabu, Tadao Yamanaka, Hidehiro Takata, Takeshi Shibagaki, Takahiko Arakawa and Shuhei Iwade (Mitsubishi Electric Corp.)
A 500-MHz, 2.0W Embedded Out-of-Order Superscalar Microprocessor
Yasuhiro Iizuka (NEC Electron Devices)
Session XII : Processors II
Chair: Yuetsu Kodama(AIST)
A 400MHz 32b Embedded Microprocessor Core with 4.0GB/S Cross-Bar Bus Switch for SoC
Masaitsu Nakajima, Takao Yamamoto, Shinji Ozaki, Tomohisa Sezaki, Tomochika Kanakogi, Takanori Furuzono, Takeshi Sakamoto, Toshihisa Aruga, Masaya Sumita, Masanori Tsutsumi, Akira Ueda and Takahiro Ichinomiya (Matsushita Electric Industrial Co., Ltd.)
A 12.8GOPS/2.1GFLOPS 8-way VLIW Embedded Multimedia Processor
Yasuki Nakamura, Hiroshi Okano, Atsuhiro Suga, Yoshimasa Takebe, Naoshi Higaki, Shin-ichirou Tago, Fumihiko Hayakawa, Tomohiro Yamana, Satoshi Imai, Hideo Miyake, Takao Sukemura, Satoshi Ado, Hiromasa Takahashi (Fujitsu Laboratories Ltd. And Fujitsu Ltd.)
Designing A Generic SoC Platform for the TriCore Processor
Kambiz Khalilian and Sagheer Ahmad (Infineon Technologies N.A.Corp.)
A Single Chip Graphics Processor for a Billion Polygons Performance
-
T.Ikedo (Hosei Univ)
Closing Remarks
Eiji Masuda, Program Committee Chair
April 20, 2002
Lecture I : Technology Scaling Challenges for Microprocessors and Systems
Chair: Toshinori Sato (Kyushu Insituite of Technology)
Speaker: Doug Burger (Univ. of Texas at Austin)
Lecture II : High Speed Optical Interconnections for the Large-Throughput Chips
Chair: Shinji Nishimura (Hitachi)
Speakers: Hiroyuki Tsuda (Keio Univ.)
Takashi Yoshikawa (NEC)
Hironori Sasaki (Oki)
Lecture III : COOL Graphics Chips
Chair: Hiroaki Kobayashi (Tohoku Univ.)
Speaker: David Kirk ( NVIDIA)