COOL Chips VI
April 16 - 18, 2003
Yokohama Joho Bunka Center, Yokohama, JAPAN
April 16, 2003
Special Session
Lecture 1: Low-Power Design of System LSI Considering Threshold Voltage and Body Bias
Chair: Makoto Nagata (Kobe University)
Speaker: Masayuki Miyazaki (Hitachi Ltd., Central Research Laboratory)
Lecture 2: Asynchronous Design
Chair: Toshinori Sato (Kyushu Institute of Technology)
Lecture 2-1: An Introduction to Asynchronous Design
Speaker: Steve Furber (The University of Manchester)
Lecture 2-2: A Fusion of Synchronous and Asynchronous Design Styles
Speaker: Takashi Nanya (University of Tokyo)
April 17, 2003
Session I : Plenary Session
Co-Chairs: Noriyoshi Ito (Oki), Keisuke Okada (Renesas Technology)
Welcome and Opening Remarks
Tadao Nakamura,
Keiichi Kawate,
Kohroh Kobayashi,
Allen J. Baum,
Keynote Presentation 1
Ultra-low Power Computation and Communication enables Ambient
Intelligence
Jan M. Rabaey (University of California, Berkeley)
Session II :
Chair: Toshinori Sato (Kyushu Institute of Technology)
Invited Presentation 1
Asynchronous Processors and On-Chip Interconnect
Steve Furber (The University of Manchester)
Session III: Specially Invited High Light Paper
Chair: Yoshiaki Hagiwara (Sony)
MICROS: A Low-cost and Low-power 2.4GHz CMOS Radio Chips for Ubiquitous Network Application
Pilsoon Choi, Hyungchul Park, Sohyeong Kim, Ilku Nam, Sungchung Park, Taewook Kim, Sangho Shin, Seokjong Park, Myungsoo Kim, Kyucheol Kang, Yeonwo Ku, Hyokjae Choi, Sook Min Park, and Kwyro Lee (KAIST)
Session IV: Poster Short Speeches
Chair: Hideharu Amano (Keio University)
Poster 1 : High Performance Powertrain Microcontroller
Yasuyuki Shimizu, Kyuotaro Nakamura, Atsuhiko Okada, Masaaki Shiotani, Yoshiki Kobayashi, Katsutoshi Yoshimura and Satoshi Inoue (Oki Electric Industrial Company)
Poster 2: A 90nm Low Power Chip design for High Performance DSP Applications
N.Venkateswaran, V.Deepak Sarathi, J.Arun Padmanabhan and Sunil Nataraj (Waran's Research Foundation)
Poster 3: EmDavid: an Embedded 3D Graphic Accelerator for Mobile Devices
Cheol-Ho Jeong, Woo-Chan Park, Jong-Chul Jeong, Hyun-Jae Woo, Kil-Whan Lee, Won-Jong Lee, Il-San Kim, Seung-Gi Lee, Jae-Hyun Kim, Tack-Don Han, and Moon-Key Lee (Yonsei University/SAMSUNG Electronics)
Poster 4: Implementation of Fundamental Logical Gates by 1-D Chaotic Elements
Toshinori Munakata and Sudeshna Sinha (Cleveland State University)
Poster 5: An Evaluation of Constructive Timing Violation via CSLA Design
Asami Tanino, Toshinori Sato and Itsujiro Arita (Kyushu Institute of Technology)
Poster 6: Low Power System-On-a-Chip for Hybrid GPS Baseband
Hwi-Sung Jung and Soo-Wan Hong (Samsung Electronics)
Poster 7: A High-speed and Low Power Hierarchical Multi-Port Cache
Zhaomin Zhu, Koh Johguchi, Hans Juergen Mattausch, Tetsushi Koide, Tai Hirakawa and Tetsuo Hironaka (Hiroshima University/Hiroshima City University)
Poster 8: Measurement and Characterization of Power Consumption of Microprocessors for Power-aware Computing
Yoshihiko Hotta, Mitsuhisa Sato, Taisuke Boku, Daisuke Takahashi and Chikafumi Takahashi (University of Tsukuba)
Poster 9: A Data Stream Distributor Chip for High-speed Routers Design: A Reconfigurable Approach
Ali EL Kateeb, Paul Richardson, and Mukul Gadde (University of Michigan)
Poster 10: A PDP-11 Compatible 16-bit Embedded Processor Core For Programmable Chip
Yoshihiro Iida and Naohiko Shimizu (Tokai University)
Poster 11: Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells
Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Sato, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka (Tokyo Metropolitan University/INNOTECH)
Poster 12: Design Variations and Performance Trade-offs by Changing Processing Rates of Functional Elements in a Reconfigurable Embedded System
Seong-Yong Ahn, Yo-Seop Hwang and Jeong-A Lee (Chosun University)
Poster 13: Core Processor/Multicontext Device Co-design
Yutaka Yamada, Katsuaki Deguchi, Naoto Kaneko and Hideharu Amano (Keio University)
Poster 14: An implementation and evaluation of the Rijndael on Async- WASMII with PCA
Yoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi and Hideharu Amano (Keio University)
Poster 15: Dynamically Reconfigurable Logic LSI designed as Fully Asynchronous System -- PCA-2
Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi and Akira Nagoya (NTT)
Session V: Low Power Designs
Chair: Kazumasa Suzuki (NEC)
A Feed-Forward Dynamic Voltage Control Algorithm for Low Power/High Quality MPEG4 on Multi-regulated Voltage CPU
Kentaro Kawakami, Hideo Ohira, Miwako Kanamori, Masayuki Miyama, Masahiko Yoshimoto (Kanazawa University)
Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications
Satoshi Misaka, Keisuke Toyama, Toshiyuki Aritsuka, Kunio Uchiyama, KazuoAisaka (Hitachi), Hiroshi Kawaguchi, Takayasu Sakurai (University of Tokyo)
A Low-Power System Solution Aimed at a Chip Multi-Processor
Masayuki Miyazaki, Goichi Ono, Hidetoshi Tanaka, Norio Ohkubo, and Takayuki Kawahara (Hitachi)
Low-Power and Highly Functional SoC Solution for Telematics Applications
Miki Hayakawa, Takashi Okada(Hitachi), Yutaka Yoshida, Takaaki Suzuki (Renesas Technology), Motoki Uehara (Hitachi ULSI Systems), Norio Nakagawa (Renesas Technology), Osamu Nishii (SuperH Japan), Kunio Uchiyama(Hitachi)
Session VI: Innovative Technologies
Chair: Makoto Ikeda (University of Tokyo)
Evaluation of a Microcontroller in Body-Tied SOI Technology
Yasuhiro Nunomura, Hisakazu Sato, Niichi Itoh, Koji Nii, Kanako Yoshida, ChikakoNakanishi, Hironobu Ito, Jingo Nakanishi, Hidehiro Takata, Yasunobu Nakase, Hiroshi Makino, Akira Yamada, Takahiko Arakawa (Renesas Technology), Tsutomu Yoshihara (Waseda University), Shuhei Iwade (Osaka Institute of Technology)
Design of the Asynchronous Embedded Controller with the Ad-hoc Control Schemes, A8051
Je-Hoon Lee, Won-Chul Lee and Kyoung-Rok Cho (Chungbuk National University)
A novel clock distribution scheme having a PVT invariance and asymptotically inherent zero skew for high density and high performance digital system
Seunghun Lee, Gyu Moon, and Jae-Kyung Wee (Hallym University)
Session VII: Mobile and Multimedia Processors
Chair: Atsushi Takahara (NTT)
Single Chip system LSI for Digital HDTV Broadcast Receivers
Kazuki Ninomiya, Shinji Ozaki, Katsumi Hoashi, Ryuji Matsuura, Hideshi Nishida, Masaaki Harada, Toshiyuki Ochiai (Matsushita Electric Industrial)
An Image Processor Capable of Block-noise-free JPEG2000 Compression with 30 frames/s for Digital Camera Applications
Yoshihiro Matsuo, Shigeyuki Okada, Kazuhiko Taketa, Tatsushi Ohyama, Yuh Matsuda, Tsugio Mori, Shin'ichiro Okada, Tsuyoshi Watanabe, Yuji Yamada, Tatsuya Ichikawa, Hideki Yamauchi, Yoshifumi Matsushita (SANYO Electric)
An Application Processor with MPEG-4 Accelerator for 3G Mobile Videophones
Kenichi Iwata, Kazushi Akie, Yukifumi Kobayashi, Hiroshi Ueda, Masaki Nobori, Masaru Hase, Hiroshi Hatae, Hiromi Watanabe, Yutaka Funabashi, Kazuyoshi Koga, Shoichi Kamae, Ken Tatezawa, Koji Yamada, Takuichiro Nakazawa, Ikuya Kawasaki (Renesas Technology)
A Single Chip MAC/PHY Processor for 5 GHz WLAN applications
K. Tsuchie, T. Fujisawa, J. Hasegawa, T. Shiozawa, T. Fujita, K. Seki-Fukuda, T.Higashi, R. Bandai, N. Yoshida, K. Shinohara, T. Watanabe, H. Hatano, K.Noguchi, T. Saito, Y. Unekawa, T. Aikawa (Toshiba)
April 18, 2003
Session VIII
Chair: Jun Iwamura (Toshiba)
Keynote Presentation 2
Rebirth of Japanese DRAM
Yukio Sakamoto (Elpida Memory)
Session IX
Chair: Seiji Yamaguchi (Matsushita)
Invited Presentation 2
Anticipation of Research and Business in Ultra Wideband (UWB) Wireless Systems
Ryuji Kohno (Yokohama National University)
Session X
Chair: Hideharu Amano (Keio University)
Invited Presentation 3
PipeRench: Energy Efficient Reconfigurable Computing with a Clean Computational Model
Herman Schmit (Carnegie Mellon University)
Session XI: High Performance and Reconfigurable Processor
Chair: Hiroaki Kobayashi (Tohoku University)
V850E2: The High Performance CPU Platform which realize Various Application Systems with Flexible Memory Configurations
Hideki Matsuyama (NEC)
VR7701: A High Performance Out-of-Order Superscalar Microprocessor with Integrated L2 Cache and Peripherals
Kuniyasu Tajima (NEC)
Dynamically Adaptive Hardware on DRP
Hideharu Amano, Akiya Jouraku (Keio University)
Late Submission: MorphoSys: a Reconfigurable Architecture Optimized for Ray Tracing
H. Du, M. Sanchez-Elez, N. Tabrizi, N. Bagherzadeh, M. Fernandez (University of California, Irvine/Universidad Complutense de Madrid)
Session XII: Compilers
Chair: Hiroshi Nakamura (University of Tokyo)
Just in Time Compiler for M32R Processors
Mamoru Sakamoto, Masato Hagiwara, Takahiro Matsuo, Akira Yamada (Renesas Technology), Shuhei Iwade (Osaka Institute of Technology)
MulTEP: MulTithreaded Embedded Processors
Panit Watcharawitch, Simon W. Moore (University of Cambridge)
Block-Based Alignment: A Mechanism to Reduce the Tag Comparisons for Low Power I-Cache
Mohan G Kabadi and Ranjani Parthasarathi (Anna University)
Session XIII: Panel Discussion
Chair and Organizer: Hiroshi Nakamura (University of Tokyo)
What is the future COOL and High-performance architecture?
Panelists:
Herman Schmit (Carnegie Mellon University),
Kazuaki Murakami(Kyushu University),
Takashi Hashimoto (Matsushita),
Takashi Miyamori (Toshiba)
Fumio Arakawa (Hitachi)
Closing Remarks
Naoki Nishi, Program Committee Chair (NEC)