COOL Chips VIII
April 20 - 22, 2005
Yokohama Joho Bunka Center, Yokohama, JAPAN
April 20, 2005
Special session 1
Chair: Fumio Arakawa (Hitachi)
Applying the EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications
Speaker: Markus Levy (EEMBC)
Special session 2
Chair: Keiji Kimura (Waseda University)
Microarchitecture-level Power Simulation: Modeling, Validation, and Design Impact
Speaker: David Brooks (Harvard University)
Special session 3
Chair: Keiji Kimura (Waseda University)
Adaptive Techniques for Power Efficient Computing
Speaker: David H. Albonesi (Cornell University)
April 21, 2005
Session I
Chair: Hajime Kubosawa (Fujitsu Lab.)
Welcome and Opening Remarks
Tadao Nakamura,
Katsuhiro Shimohigashi,
Lily Jow,
Hajime Imai,
Shigemi Sato
Keynote Presentation 1
A Revolution in System-On-Chip Automation
Chris Rowen (Tensilica, Inc.)
Session II
Chair:Jiro Naganuma (NTT)
Invited Presentation 1
Multimedia Processor-based Platform for a Wide Range of Digital Consumer Electronics
Tokuzo Kiyohara (Matsushita Electric Industrial Co., Ltd.)
Session III: Low power system
Chair: Yoshio Hirose (Fujitsu Lab.)
A Flexible 8-bit Asynchronous Microprocessor Based on Low-Temperature Poly-Silicon (LTPS) TFT Technology
Nobuo Karaki, Takashi Nanmoto, Hiroaki Ebihara, Satoshi Inoue, and Tatsuya Shimoda (Seiko Epson Corp.)
Novel Power Reduction Methods for the CISC-type Embedded Asynchronous Processor
Je-Hoon Lee, Young-Il Lim, and Kyoung-Rok Cho (Chungbuk National University)
Time Revising Robust Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications
Satoshi Misaka, Hiroshi Kawaguchi, and Takayasu Sakurai (Hitachi / The University of Tokyo)
Error Diffusion in Low Power Display Sub-system
Xiaoying He, Luhong Liang, and Ying Jia (Intel)
Session IV: Poster Short Speeches
Chair: Kimiyoshi Usami (Shibaura Institute of Technology)
Poster 1: A Hardware Design Verification Methodology Using Signal Transitions and Transactions
Nobuyuki Ohba and Kohji Takano (IBM Japan Ltd.)
Poster 2: Implementation of AES on the Dynamic Reconfigurable Processor
Shohei Abe, Yohei Hasegawa, and Hideharu Amano (Keio University)
Poster 3: A UWB Radio System Architecture Using Mixed-mode Memory
Sungwon Chung, Woomin Hwang, Youngwoo Park, and Kyu Ho Park (KAIST)
Poster 4: End-to-end QoS Based Low Power LASeR Transcoding Dipnarayan
Guha, Qonita Muhammad Shahab, and Jun Kyun Choi (Information and Communications University)
Poster 5: A High Level SoC Energy Analysis Method with Good Accuracy Using Cycle Accurate Simulation
Ana Abril, Habib Mehrez, Frederic Petrot, Jean Gobert, and Carolina Miro (University Paris VI / Philips Applied Technologies)
Session V: Chip multiprocessors
Chair: Naoki Nishi (NEC)
Multi-Tasking Parallel Method on MP211 Multicore Application Processor
Junji Sakai, Hiroaki Inoue, Tsuyoshi Abe, Noriaki Suzuki, Masaki Uekubo, Yoshiyuki Ito, Kenji Suzuki, Masaki Kondo, and Masato Edahiro (NEC)
Embedded Single-chip Multiprocessor Using Coarse-grain Parallelism
Shinichiro Tago, Tetsuyoshi Shiota, Yasuki Nakamura, Hiroshi Okano, Fumihiko Hayakawa, Satoshi Imai, Atsushi Tanaka, Hideo Miyake, Atsuhiro Suga, and Hiromasa Takahashi (Fujitsu Labs.)
A Low-power Processor Based on Asymmetric Multi-CPU Architecture for SoCs
Masato Hagiwara, Isao Minematsu, Takahiro Yamashita, Yoshihide Komatsu, Tetsuya Fujimoto, Toshiro Tsukada, and Koichiro Ishibashi (STARC)
Session VI: Panel Discussion
Chair: Yoshiaki Hagiwara (Sony)
Will the Future Processors and the Target Market still be Driven by the
Moore’s Law?
April 22, 2005
Session VII
Chair: Makoto Ikeda (The University of Tokyo)
Keynote Presentation 2
Cell Future
Masakazu Suzuoki (Sony Computer Entertainment America, Inc.)
Session VIII
Chair: Kunio Uchiyama (Hitachi)
Invited Presentation 2
All about the Cell Processor
Peter Hofstee (IBM Austin)
Session IX
Chair: Masato Suzuki (Matsushita Electric Ind.)
Invited Presentation 3
SoC Design Verification Strategies
Chong-Min Kyung (Korea Advanced Institute of Science and Technology)
Session X: Wireless and signal processing
Chair: Kiat-Seng Yeo (Nanyang Technological University)
A Memory-efficient and Energy-aware Pipeline Architecture for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000
Bing-Fei Wu, Chung-Fu Lin, and Pei-Kung Huang (National Chiao Tung
University)
Implementation of Application-specific Signal Processor for High-speed OFDM Systems
Jeong H. Lee, Myung H. Sunwoo, and Sung K. Oh (Ajou University)
sys-FIR: A Compiler for Evaluating VLSI Performance Metrics of Reduced Adder Cost FIR Filters
Sharma Udit, Fei Xu, Chip-Hong Chang, Ching-Chuen Jong, and Kiat-Seng Yeo (Nanyang Technological University)
A Digital Beam Forming LSI for Throughput and Area Coverage Enhancement of 802.11a/b/g WLAN
Kuniaki Ito, Hideo Kasami, Kazumi Sato, Tsuguhide Aoki, Ren Sakata, Koji Akita, Tsuyoshi Kogawa, Hironori Uchikawa, and Yasuo Unekawa (Toshiba)
Session XI: Reconfigurable systems and memory
Chair: Yuetsu Kodama (AIST)
A Low Power Data Cache for Embedded Processors
Saibhushan Musalappa, Shivakumar Sundaram, and Yul Chu (Mississippi State University)
A Small Flip-flop Cache with Hardware Pre-fetch for Low-power Access of On-chip Flash Memory
Teppei Hirotsu, Yuichi Abe, Hiromichi Yamada, Seiji Takeuchi, Takeshi Kataoka, and Yasuo Sugure (Hitachi / Renesas Technology)
Programmable Logic Device with an 8-stage Cascade of 64K-bit Asynchronous SRAMs
Kazuyuki Nakamura, Tsutomu Sasao, Munehiro Matsuura, Katsumasa Tanaka,Kenichi Yoshizumi, Hui Qin, and Yukihiro Iguchi (Kyushu Institute of Technology / Meiji University)
Solicited Presentation
Dynamically Calibrating Clock Rate for FPGAs
Oskar Mencer, Jacob A. Bower, Wayne Luk, Michael J. Flynn, and Martin Morf(Imperial College London / Stanford University)
Session XII: Circuits for low power
Chair: Makoto Ikeda (The University of Tokyo)
A Wide-range PLL-based Clock Generator Having Fast-relocking for Low Power and Multiple Clock Domains
Tae-Jin Hwang, Won-Young Jung, Seong-Su Park, Yong-Ju Kim, and Jae-Kyung Wee (School of Electronics Engineering Soongsil Univ.)
Novel Single/Double-edge Triggered Pulse Generator Flip-flop for Low Power Applications
Khaing Yin Kyaw, Yeo Kiat Seng; Goh Wang Ling, and Phyu Myint Wai (Nanyang Technological University)
Session XIII: High performance processors
Chair: Fumio Arakawa (Hitachi)
Solicited Presentation
The Power Conscious Design of the Synergistic Processor Element of a CELL Processor
Osamu Takahashi, Toru Asano, Russ Cook, Scott Cottier, Omar Delgado, Sang H.Dhong, Brian Flachs, Koji Hirairi, Atsushi Kawasumi, Jens Leenstra, Takashi Machida, Brad Michael, Hideaki Murakami, Hiroaki Murakami, Takaaki Nakazato, Hiroo Nishikawa, Hiromi Noro, Hwa-Joon Oh, Shoji Onishi, Juergen Pille, Jieming Qi, Joel Silberman, Naoka Yano, Suksoon Yong, Dieter Wendel, and Michael White (IBM / Sony/ Toshiba)
Low Power Design in 11FO4 Embedded SRAM for the Synergistic Processor Element of a CELL Processo
Toru Asano, Takaaki Nakazato, Sang H. Dhong, Atsushi Kawasumi, Joel
Silberman, Osamu Takahashi, Michael White, Hiroshi Yoshihara, and Scott Cottier (IBM / Toshiba / Sony)
A CELL Software Platform for Digital Media Application
Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, and Haruyuki Tago (Toshiba)
Limit of Thread-level Parallelism on Partitioning Levels and Speculations in Non-numerical Programs
Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, and Toshio Shimada (NagoyaUniversity)
Distributed Speculative Memory Forwarding
Hidetsugu Irie, Naoya Hattori, Masanori Takada, Naoya Hatta, Takashi Toyoshima, and Shuichi Sakai (The University of Tokyo / Japan Science and Technology Agency / Hitachi)
Closing Remarks
Chair: Makoto Ikeda (The University of Tokyo)
Kunio Uchiyama, Program Committee Chair