Here, COOL Chips XVII Program [pdf] is uploaded. (As of April 14, 2014)
Monday, April 14, 2014 Main Hall (7th Floor)
| 13:00-14:30 | Special Invited Lecture 1 Co-chairs: Hiroyuki Tomiyama (Ritsumeikan University) Yuko Hara-Azumi (Tokyo Institute of Technology) |
| 13:00-14:30 | Application-Specific Processors – Addressing High-Performance Computing Challenges Masaaki Ideno (Synopsys)(Abstract, Bio) |
| 14:30-15:00 | Break |
| 15:00-16:30 | Special Invited Lecture 2 Co-chairs: Hiroyuki Tomiyama (Ritsumeikan University) Yuko Hara-Azumi (Tokyo Institute of Technology) |
| 15:00-16:30 | Vivado HLS – High Level Synthesis for FPGA Igor A. Kostarnov (Xilinx Japan, Japan) (Abstract, Bio) |
| 16:30-17:00 | Break |
| 17:00-18:30 | Special Invited Lecture 3 Co-chairs: Hiroyuki Tomiyama (Ritsumeikan University) Yuko Hara-Azumi (Tokyo Institute of Technology) |
| 17:00-18:30 | A New Generation of Parallel Processing: Altera FPGAs as Accelerators for an OpenCL Platform Dirk Seynhaeve (Altera, USA) (Abstract, Bio) |
Tuesday, April 15, 2014 Main Hall (7th Floor)
| 9:30-9:50 | Session I: Welcome and Opening Remarks Chair: Hiroyuki Igura (NEC) |
| Hiroaki Kobayashi, Chair of the Organizing Committee Takatomo Enoki, President of the Electronics Society, IEICE Seiji Murozono, Director of the Economic Affairs Bureau, City of Yokohama |
| 9:50-10:40 | Session II: Keynote Presentation 1 Co-chairs: Masato Suzuki (Panasonic) Yukinori Sato (JAIST) |
| 9:50-10:40 | Programming the Internet of Things―Combining Internet and Embedded Programming Models Michael McCool (Intel, USA) (Abstract, Bio) |
| 10:40-10:50 | Break |
| 10:50-11:40 | Session III: Keynote Presentation 2 Co-chairs: Hideharu Amano (Keio University) Akihiko Hashiguchi (Sony) |
| 10:50-11:40 | Future Trend and the chance of Reconfigurable Computing Jay Kim (Samsung, Korea) (Abstract, Bio) |
| 11:40-11:50 | Break |
| 11:50-12:20 | Session IV : Poster Short Speeche Chair: Koji Hashimoto (Fukuoka University) |
| 12:20-13:20 | Lunch Time Break |
| 13:20-13:40 | Poster Open: 7th floor poster show room |
| 13:40-14:30 | Session V: Keynote Presentation 3 Co-chairs: Koji Takano (IBM) Yusuke Nitta (Renesas) |
| 13:40-14:30 | SyNAPSE: Foundation of Future Neuronsynaptic Computing System Jun Sawada (IBM, USA) (Abstract, Bio) |
| 14:30-15:30 | Break (Poster Open: 7th floor poster show room) |
| 15:30-16:20 | Session VI: Multi/Many Core Co-chairs: Hiroyuki Takizawa (Tohoku University) Shintaro Izumi (Kobe University) |
| Establishing a standard interface between multi-manycore and software tools – SHIM Masaki Gondo1, Fumio Arakawa2, Masato Edahiro2 (1eSOL, 2Nagoya University) |
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| Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Yuta Suzuki1, Kota Sata2, Junichi Kako2, Kohei Yamaguchi1, Fumio Arakawa1, and Masato Edahiro1 (1Nagoya University, 2Toyota Motor) |
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| 16:20-16:30 | Break |
| 16:30-18:30 | Session VII: Panel Discussions |
| 16:30-18:30 | Topics: “Toward Wearable Computing Era, How COOL Chip Architectures and Tools will Evolve? “ Organizer / Modelator : Fumio Arakawa (Nagoya University)(Abstract, Bio) Panelist : Michael McCool (Intel, USA), Soojung Ryu (Samsung, Korea), Shumpei Kawasaki (Open Core Foundation, USA), Hiroaki Tobita (Sony) |
| 18:30-19:00 | Break |
| 19:00-21:00 | Banquet |
Wednesday, April 16, 2014 Main Hall (7th Floor)
| 9:30-10:20 | Session VIII: Keynote Presentation 4 Co-chairs: Fumio Arakawa (Nagoya University) Yuki Kobayashi (Renesas Electronics) |
| 9:30-10:20 | Open Source Hardware Development Model and Old CPU Shumpei Kawasaki (Open Core Foundation, USA) (Abstract, Bio) |
| 10:20-10:40 | Break |
| 10:40-11:20 | Session IX: Memories Co-chairs: Masanori Muroyama (Tohoku University) A. Hashiguchi (Sony) |
| Language Runtime Support for NVM/DRAM Hybrid Main Memory Gaku Nakagawa and Shuichi Oikawa (University of Tsukuba) |
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| A Low Power DRAM Refresh Control Scheme in Hybrid Memory Cube (short) Ying Wang, Yinhe Han, Huawei Li (Chinese Academy of Sciences) |
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| 11:20-11:30 | Break |
| 11:30-12:35 | Session X: Dependability Co-chairs: Akram Ben Ahmed (The University of Aizu) Hajime. Shimada (Nagoya University) |
| A Flexibly Fault-Tolerant FU Array Processor and its Self-Tuning Scheme to Locate Permanently Defective Unit Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka (NAIST) |
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| A Globally Asynchronous Locally Synchronous DMR Architecture for Aggressive Low-Power Fault Toleration Yuttakon Yuttakonkii, Jun Yao, Yasuhiko Nakashima (NAIST) |
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| Kernel Data Race Detection using Debug Register in Linux (short) Yunyun Jiang, Yi Yang, Tian Xiao, Tianwei Sheng, Wenguang Chen (Tsinghua University, China) |
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| 12:35-13:40 | Lunch Time Break |
| 13:40-14:30 | Session XI: Keynote Presentation 5 Co-chairs: Ryusuke Egawa (Tohoku University) Koyo Nitta (NTT) |
| 13:40-14:30 | Low Power High Performance Processors for Quantum Computing Colin Williams (D-wave Systems, Canada)(Abstract, Bio) |
| 14:30-14:40 | Break |
| 14:40-15:30 | Session XII: Low-power circuit techniques Co-chair: Makoto Ikeda (University of Tokyo), Akihiko Hashiguchi (Sony) |
| A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology Koichiro Ishibashi1, Nobuyuki Sugii2, Kimiyoshi Usami3, Hideharu Amano4, Kazutoshi Kobayashi5, Cong-Kha Pham1, Hideki Makiyama2, Yoshiki Yamamoto2, Hirofumi Shinohara2, Toshiaki Iwamatsu2, Yasuo Yamaguchi2, Hidekazu Oda2, Takumi Hasegawa2, Shinobu Okanishi2, Hiroshi Yanagita2, Shiro Kamohara2, Masaru Kadoshima2, Keiichi Maekawa2, Tomohiro Yamashita2, Duc-Hung Le1, Takumu Yomogita1, Masaru Kudo3, Kuniaki Kitamori4, Shuya Kondo5, Yuuki Manzawa5 (1The University of Electro-Communications, 2Low-power Electronics Association & Project, 3Shibaura Institute of Technology, 4Keio University, 5Kyoto Institute of Technology) |
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| Embedded SRAM and Cortex-M0 Core with Backup Circuits Using a 60-nm Crystalline Oxide Semiconductor for Power Gating Hikaru Tamura1, Kiyoshi Kato1, Takahiko Ishizu1, Tatsuya Onuki1, Wataru Uesugi1, Takuro Ohmaru1, Kazuaki Ohshima1, Hidetomo Kobayashi1, Seiichi Yoneda1, Atsuo Isobe1, Naoaki Tsutsui1, Suguru Hondo1, Yasutaka Suzuki1, Yutaka Okazaki1, Tomoaki Atsumi1, Yutaka Shionoiri1, Yukio Maehashi1, Gensuke Goto1, Masahiro Fujita2, James Myers3, Pekka Korpinen4, Jun Koyama1, Yoshitaka Yamamoto1, Shunpei Yamazaki1 (1Semiconductor Energy Laboratory, 2The University of Tokyo, 3ARM, 4Nokia) |
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| 15:30-15:40 | Break |
| 15:40-16:55 | Session XIII: Power Optimization Co-hairs: Jun Yao (NAIST) Masaki Gondo (eSOL) |
| Aggressive Use of Deep Sleep Mode in Low Power Embedded Systems Jun ’ichi Segawa, Yusuke Shirota, Koichi Fujisaki, Tetsuro Kimura and Tatsunori Kanai (Toshiba) |
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| An Energy Optimization Method for Vector Processing Mechanisms Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi (Tohoku University) |
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| A Fine Grained Power Management Supported by Just-In-Time Compiler Motoki Wada, Mikiko Sato, Mitaro Namiki (Tokyo University of Agriculture and Technology) |
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| 16:55-17:05 | Break |
| 17:05-17:45 | Session XIV: NoC Co-chairs: Sugako Otani (Renesas) Yasutaka Wada (UEC) |
| A Task-level Pipelined Many-SIMD Augmented Reality Processor with Congestion-aware Network-on-Chip Scheduler Gyeonghoon Kim, Seongwook Park, Kyuho Lee, Youchang Kim, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Junyoung Park, and Hoi-Jun Yoo (KAIST) |
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| A low power NoC router using the marching memory through type (short) Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura (Keio University) |
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| 17:45-18:05 | Poster Award and Closing Remarks Makoto Ikeda, Program Committee Co-chair (The University of Tokyo) |