Advance Program

Here, COOL Chips 21 Final Program [pdf] is uploaded. (As of Apr 16, 2018)

 

Wed. April 18, 2018　　　Main Hall (7th Floor)
13:30-15:00Special Invited Lecture 1
Chair: T. Ishihara (Kyoto Univ.)
"Energy-Efficient and Energy-Scalable Processing ? Meeting the Varied Needs of the Internet of Things at Its Edge"
Massimo Alioto (National University of Singapore, Singapore) (Abstract, Bio)
15:00-15:30Break
15:30-17:00Special Invited Lecture 2
Chair: T. Ishihara (Kyoto Univ.)
"High-Power-Efficiency Implementation of Neuromorphic Computing Systems with Memristors"
Yiran Chen (Duke University, USA) (Abstract, Bio)
17:00-17:15Break
17:15-18:05Keynote Presentation 1
Co-Chairs: S. Takamaeda (Hokkaido U.), M. Suzuki (Socionext)
"Tensor Processing Unit: A processor for neural network designed by Google"
Kaz Sato (Google Inc. ) (Abstract, Bio)

 

Thu. April 19, 2018　　　Main Hall (7th Floor)
9:30-9:50Session I Welcome and Opening Remarks
Co-chairs: Yuki Kobayashi (NEC), Hiroki Matsutani (Keio Univ.)
Hideharu Amano, Chair of the Organizing Committee
Hironori Kasahara, President of IEEE/CS
Allen J. Baum, Chair of IEEE/CS TCMM
Hiroyuki Uenohara, President of IEICE/ES
9:50-10:40Session II Keynote Presentation 2
Co-chairs: Ryusuke Egawa (Tohoku Univ.), Yuki Kobayashi (NEC)
"AMD EPYC Microprocessor Architecture"
Jay Fleischman (Advanced Micro Devices, USA) (Abstract, Bio)
11:00-11:50Session III Keynote Presentation 3
Co-chairs: Megumi Ito (IBM), Takuya Nakaike (IBM)
"Designing Deep Neural Network Accelerators with Analog Memory  A Device and Circuit Perspective"
Pritish Narayanan (IBM Research - Almaden, USA) (Abstract, Bio)
11:50-12:00Break
12:00-12:30Session IV: Poster Short Speeches
Chair: Koji Hashimoto (Fukuoka Univ.)
12:30-13:50Lunch Time Break
13:50-14:00Poster Open: 7th floor poster show room
14:00-14:50Session V Keynote Presentation 4
Co-chairs: Yasutaka Wada (Meisei Univ.), Koyo Nitta (NTT)
"Designing a Power and Energy Stack for Exascale Systems"
Martin Schulz (Technische Univ. Munchen) (Abstract, Bio)
14:50-15:40Break (Poster Open: 7th floor poster show room)
15:40-16:20Session VI: Design Methodologies
Co-Chairs: Yuichiro Shibata (Nagasaki Univ.), Kyoung-Rok Cho (Chungbuk National Univ.)
15:40-16:05"Design Automation Methodology of a Critical Path Monitor for Adaptive Voltage Controls"
Ryosuke Kazami, Hayate Okuhara, Hideharu Amano (Keio Univ.)
16:05-16:20"3D-Cool: Design and Development of Adaptive Thermal-Aware Three-Dimensional NoC-Based Multiprocessor Chip"
Vinod Pangracious, Ranjita Dash, Ashok Kumar Turuk (American Univ. in Dubai, UAE)
16:20-16:35Break
16:35-18:05Session VII: Panel Discussions
Topics: "Challenges to the Scaling Limits: How Can We Achieve Sustainable Power-Performance Improvements?"
Organizer & Moderator: Koji Inoue (Kyushu Univ.) (Abstract, Bio)
Panelists: Takuya Araki (NEC)
Takumi Maruyama (Fujitsu)
Pritish Narayanan (IBM Research - Almaden)
Takashi Oshima (Hitachi)
Martin Schulz (Technische Univ. Munchen)
18:05-18:30Break
18:30-20:30Banquet

 

Fri, April 20, 2018　　　Main Hall (7th Floor)
9:30-10:20 Session VIII Keynote Presentation 5
Co-chairs: Yukinori Sato (Toyohashi Univ. of Technology), Hiroki Matsutani (Keio Univ.)
"Multiscale Dataflow ASICs – Easy, Fast, Low Cost"
Oskar Mencer (Maxeler Technologies / Imperial College London, UK) (Abstract, Bio)
10:20-10:40Break (Poster Open: 7th floor poster show room)
10:40-11:55Session IX: Neural Networks
Co-chairs: Yuetsu Kodama (Riken), Sugako Otani (Renesas Electronics)
10:40-11:05"XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks"
Andrawes Al Bahou, Geethan Karunaratne, Renzo Andri, Lukas Cavigelli, Luca Benini (ETH, Switzerland)
11:05-11:30"ecTALK: Energy Efficient Coherent Transprecision Accelerators - The Bidirectional Long Short-Term Memory Neural Network case"
Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner (IBM, Switzerland)
11:30-11:55"EMAXVR: A Programmable Accelerator Employing Near ALU Utilization to DSA"
Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima (NAIST)
11:55-13:20Lunch Time Break
13:20-14:10Session X Keynote Presentation 6
Co-chairs: Hideharu Amano (Keio Univ.), Kunio Uchiyama (Hitachi)
"Unlocking Hidden Performance: Examples from FPGA-Based Neural Nets"
Ephrem Wu (Xilinx, USA) (Abstract, Bio)
14:10-14:30Break (Poster Open: 7th floor poster show room)
14:30-15:35Session XI: Signal Processing
Co-Chairs: Masanori Muroyama (Tohoku Univ.), Yasutaka Wada (Meisei Univ.)
14:30-14:55"Data Selection and De-noising Based on Reliability for Long-Range and High-Pixel Resolution LiDAR"
Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto (Toshiba)
14:55-15:20"A Programmable Analog Calculation Unit for Vector Computations"
Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yosuhiko Nakashima (NAIST)
15:20-15:35"Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator"
Mathieu Coustans, Thomas Eberhardt, Stephanie Salgado, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Maher Kayal (EPFL, U. Grenoble Alpes, EM Microelectronic)
15:35-15:55Break
15:55-17:40Session XII: Processor Architectures
Co-chairs: Hajime Shimada (Nagoya Univ.), Kotaro Shimamura (Hitachi)
15:55-16:20"An Energy-aware Set-level Refreshing Mechanism for eDRAM Last-Level Caches"
Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.)
16:20-16:45"Power Performance Analysis of ARM Scalable Vector Extension"
Tetsuya Odajima, Yuetsu Kodama, Mitsuhisa Sato(Riken)
16:45-17:00"A Two-stage-pipeline CPU of SH-2 Architecture Implemented on FPGA and SoC for IoT, Edge AI and Robotic applications"
Kesami Hagiwara, Shumpei Kawasaki, Hayato Nomura (UEC, SH Consulting, Japan, Viet Nam, USA)
17:00-17:40(Invited Presentation) "Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware"
Yunsup Lee (SiFive, USA) (Abstract, Bio)
17:40-18:00Poster Award and Closing Remark
Makoto Ikeda, Program Committee Co-chair (Univ. of Tokyo)