IEEE COOL Chips 23 Final Program [pdf] including poster presentations is uploaded here.
Wed. April 15, 2020
| 9:00-10:30 | Special Invited Lecture 1 Co-chairs: Takatsugu Ono (Kyushu Univ.), Hiroki Matsutani (Keio Univ.) |
| "Evolving Hardware Security Landscape in the AI Era", Guru Prasadh Venkataramani (The George Washington University, USA) (Abstract, Bio) |
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| 10:30-11:00 | Break |
| 11:00-12:30 | Special Invited Lecture 2 Co-chairs: Takatsugu Ono (Kyushu Univ.), Hiroki Matsutani (Keio Univ.) |
| "Using AI to Bridge the Gap Between AI Models and the Hardware of Today and Tomorrow", Luis Ceze (University of Washington, USA)(Abstract, Bio) |
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| 12:30-14:00 | Lunch Break |
| 14:00-15:40 | Poster Session Co-chairs: Koji Hashimoto (Fukuoka Univ.), Yuki Kobayashi (NEC) |
Thu. April 16, 2020
| 9:00-9:10 | Session I Welcome and Opening Remarks Co-chairs: Yuki Kobayashi (NEC), Hiroki Matsutani (Keio Univ.) |
| Kunio Uchiyama, Chair of the Organizing Committee Jose Renau, Chair of IEEE/CS TCMM Tugumichi Shibata, President of IEICE/ES |
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| 9:10-10:00 | Session II Keynote Presentation 1 Co-chairs: Yasutaka Wada (Meisei Univ.), Yukinori Sato (Toyohashi Univ. of Tech.) |
| [CANCELED] Aaron Smith (Microsoft, USA) (Abstract, Bio) |
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| 10:00-10:10 | Break |
| 10:10-11:00 | Session III Keynote Presentation 2 Co-chairs: Kunio Uchiyama (AIST), Yasushi Inoguchi (JAIST) |
| "Disruptive Evolutions: Technology Challenges and Countermeasures", Shinichi Yoshioka (Renesas, Japan)(Abstract, Bio) |
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| 11:00-11:10 | Break |
| 11:10-12:00 | Session IV Keynote Presentation 3 Co-chairs: Tohru Ishihara (Nagoya Univ.), Yasuo Unekawa (Toshiba) |
| How to Uplift the World with "Memory", Kenichi Mori (Kioxia, Japan)(Abstract, Bio) |
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| 12:00-13:00 | Lunch Time Break |
| 13:00-13:40 | Session V Invited Presentation 1 Co-chairs: Ryuichi Sakamoto (Univ. of Tokyo), Atsutake Kosuge (Hitachi) |
| "Virtualization for Non-volatile Memory Devices", Takahiro Hirofuchi (AIST, Japan) (Abstract, Bio) |
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| 13:40-14:10 | Break |
| 14:10-15:25 | Session VI: Application specific processors and system Co-chairs: Yuichiro Shibata (Nagasaki Univ.), Yasutaka Wada (Meisei Univ.), Takumi Uezono (Hitachi) |
| 14:10-14:35 | "A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers", Junichiro Kadomoto, Hidetsugu Irie and Shuichi Sakai (Univ. of Tokyo, Japan) |
| 14:35-15:00 | "Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control", Shota Nakabeppu, Yosuke Ide, Masahiko Takahashi, Yuta Tsukahara, Hiromi Suzuki, Haruki Shishido and Nobuyuki Yamasaki (Keio Univ., Japan) |
| 15:00-15:25 | "MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture", Yasuhiro Mochida, Takahiro Yamaguchi and Ken Nakamura (NTT, Japan) |
| 15:25-15:45 | Break |
| 15:45-16:35 | Session VII: Cool Software Co-chairs: Hiroyuki Takizawa (Tohoku Univ.), Shunsuke Sasaki (Toshiba Electoronic Devices & Storage), Atsutake Kosuge (Hitachi) |
| 15:45-16:10 | "User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement", Jisu Kwon, Moon Gi Seok and Daejin Park (Kyungpook National Univ., Korea, Nanyang Technological Univ., Singapore) |
| 16:10-16:35 | "XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs", Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank Kagan Gürkaynak, Christoph Hagleitner, Cristiano Malossi and Luca Benini (IBM research, Integrated Systems Lab., Switzerland, Univ. of Bologna, Italy) |
| 16:35-16:55 | Break |
| 16:55-17:45 | Session VIII: Low Power Processors Co-chairs: Kotaro Shimamura (Hitachi), Fumio Arakawa (Nagoya Univ.), Takumi Uezono (Hitachi) |
| 16:55-17:20 | "A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan", Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Räm äkkö, Sofia Mäkikyrö and Lauri Koskinen (Minima Processor, Univ. of Turku, Finland) |
| 17:20-17:45 | "A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM", Dennis Walter, Andre Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csazar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich and Sebastian Höppner (Racyics GmbH, Germany) |
Fri, April 17, 2020
| 9:00-9:40 | Session IX Invited Presentation 2 Co-chairs: Yuki Kobayashi (NEC), Koyo Nitta (NTT), Hiroki Matsutani (Keio Univ.) | |||
| Intel Optane™ Data Center Persistent Memory - A True Breakthrough to Break the Traditional MemoryStorage Technologies Barriers", Jane Jianping Xu / Kaushik Balasubramanian (Intel, USA) (Abstract, Bio) | ||||
| 9:40-10:00 | Break | |||
| 10:00-10:50 | Session X: Memory Systems Co-chairs: Hajime Shimada (Nagoya Univ.), Ryohei Kobayashi (Univ. of Tsukuba), Yutaka Uematsu (Hitachi) | |||
| 10:00-10:25 | "Tileable Monolithic ReRAM Memory Design", Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob and Donald Yeung (Univ. of Maryland, Crossbar Inc., USA) | |||
| 10:25-10:50 | "Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture", Masayuki Sato, Xue Hao, Kazuhiko Komatsu and Hiroaki Kobayashi (Tohoku Univ., Japan) | |||
| 10-50-11:00 | Break | |||
| 11:00-11:50 | Session XI: Keynote Presentation 4 Co-chairs: Masato Suzuki (Socionext), Takuya Nakaike (IBM) | |||
| "An Extremely Quantized Deep Neural Network Accelerator for Edge Devices", Hiroyuki Tokunaga (LeapMind, Japan)(Abstract, Bio) | ||||
| 11:50-13:20 | Lunch Time Break | |||
| 13:20-14:35 | Session XII: Accelerators Co-chairs: Sugako Otani (Renesas Electronics), Salita Sombatsiri (NEC), Yutaka Uematsu (Hitachi) | |||
| 13:20-13:45 | "A Novel In-DRAM Accelerator Architecture for Binary Neural Network", Haerang Choi, Yosep Lee, Jae-Joon Kim and Sungjoo Yoo (Seoul National Univ., SK Hynix, POSTECH, Korea) | |||
| 13:45-14:10 | "Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization", Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki and Yasuo Kanda (Shibaura Institute of Technology, Keio Univ, Sony Semiconductor Solutions Corp., Japan) | |||
| 14:10-14:35 | "An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection", Takuya Sakuma and Hiroki Matsutani (Keio Univ., Japan) | |||
| 14:35-14:45 | Poster Award and Closing Remark Makoto Ikeda, Program Committee Co-chair (Univ. of Tokyo) |