Here, COOL Chips XIX Final Program [pdf] is uploaded. (As of April 15, 2016)
Attention!!
Time table of April 22, Friday has been changed (on Apr 15, 2016).
Time table of April 22, Friday has been changed (on Apr 15, 2016).
Wed. April 20, 2016 Main Hall (7th Floor)
| 13:30-15:00 | Special Invited Lecture 1 Chair: T. Ishihara (Kyoto Univ.) |
| Inter/Intra-Chip Optical Networks Jiang Xu (Hong Kong University of Science and Technology)(Abstract, Bio) |
|
| 15:00-15:30 | Break |
| 15:30-17:00 | Special Invited Lecture 2 Chair: T. Ishihara (Kyoto Univ.) |
| Architectural Approaches to using STT-RAM for Low-Power Caches Kiyoung Choi (Seoul National University) (Abstract, Bio) |
Thu. April 21, 2016 Main Hall (7th Floor)
| 9:30-9:50 | Session I: Welcome and Opening Remarks |
| Hiroaki Kobayashi, Chair of the Organizing Committee | |
| 9:50-10:40 | Session II: Keynote Presentation 1 Co-chairs: H. Amano (Keio Univ.), K. Uchiyama (Hitachi) |
| Sub-pj per Operation Scalable Computing – the Next Challenge Luca Benini (ETHZ, Switzerland) (Abstract, Bio) |
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| 10:40-11:30 | Session III: Keynote Presentation 2 Co-chairs: Y. Kobayashi (NEC), M. Suzuki (Socionext) |
| Power Optimization Leveraging FPGA and Voltage Regulator Chip Co-Design Ashraf Lotfi (Intel, USA) (Abstract, Bio) |
|
| 11:30-11:40 | Break |
| 11:40-12:10 | Session IV : Poster Short Speech Chair: K. Hashimoto (Fukuoka University) |
| 12:10-13:10 | Lunch Time Break |
| 13:10-14:10 | Poster Open: 7th floor poster show room |
| 14:10-15:00 | Session V: Keynote Presentation 3 Co-chairs: A. Hashiguchi (Sony), Y. Hirose (Fujitsu Labs.) |
| Modality of CMOS Image Sensor Competition Teruo Hirayama (Sony, Japan) (Abstract, Bio) |
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| 15:00-15:50 | Session VI: Keynote Presentation 4 Co-chairs: Y. Unekawa (Toshiba), C. Takahashi (Renesas System Design) |
| The Multiscale Dataflow Computing Chip Oskar Mencer (Imperial College London and Maxeler Technologies, UK) (Abstract, Bio) |
|
| 15:50-16:05 | Break |
| 16:05-17:20 | Session VII: Recognition Co-chairs: T. Azumi (Osaka Univ.), Y. Shibata (Nagasaki Univ.) |
| 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-Efficient Parallel and Sequential Digital Processing Davide Rossi(University Of Bologna), Antonio Pullini (ETH Zurich), Igor Loi (University Of Bologna), Michael Gautschi, Frank Kagan Gurkaynak (ETH Zurich), Adam Teman, Jeremy Constantin, Andres Burg (EPFL), Ivan Miro-Panades, Edith Beigne , Fabien Clermidy (CEA LETI), Fady Abouzeid, Philippe Flatresse (ST Microelectronics), and Luca Benini (University Of Bologna) |
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| A 1.1mW 32-thread Artificial Intelligence Processor with 3-level Transposition Table and On-chip PVT Compensation for Autonomous Mobile Robots Youchang Kim, Dongjoo Shin, Jinsu Lee, and Hoi-Jun Yoo (KAIST) |
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| An Energy-Efficient Parallel Multi-Core ADAS Processor with Robust Visual Attention and Workload-Prediction DVFS for Real-Time HD Stero Stream Kyuho Lee, Kyeongryeol Bong, Changhyeon Kim (KAIST), Junyoung Park (UX Factory), and Hoi-Jun Yoo (KAIST) |
|
| 17:20-17:30 | Break |
| 17:30-19:00 | Session VIII: Panel Discussions |
| Topics: “Computing and Communication Evolution for IoT Innovations“ Organizer / Modelator : Hiroaki Nishi (Keio University, Japan)(Abstract) Panelist : Jiang Xu （Hong Kong University of Science and Technology), Luca Benini （ETHZ), Michael McCool (Intel), Toshitsugu Sakamoto (NEC), Shingo Fujimoto (Fujitsu) |
|
| 19:00-19:30 | Break |
| 19:30-21:30 | Banquet |
Fri, April 22, 2016 Main Hall (7th Floor)
| 9:30-10:20 | Session IX: Keynote Presentation 6 Co-chairs: K. Nitta (NTT Electronics), R. Egawa (Tohoku Univ.) |
| New Frontiers in Computing Michael McCool (Intel, USA) (Abstract, Bio) |
|
| 10:20-10:40 | Break |
| 10:40-11:20 | Session X: Memory Co-chairs: H. Shimada (Nagoya Univ.), H. Matsumura (Fujitsu Labs.) |
| A Cache Partitioning Mechanism to Protect Shared Data for CMPs Masayuki Sato, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi (Tohoku University) |
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| Powering-off DRAM with Aggressive Page-out to Storage-class Memory in Low Power Virtual Memory System Yusuke Shirota, Shiyo Yoshimura, Satoshi Shirai, and Tatsunori Kanai (Toshiba) |
|
| 11:20-11:40 | Break |
| 11:40-12:45 | Session XI: Low Power Processing Co-chairs: S. Izumi (Kobe Univ.), K. Shimamura (Hitachi) |
| MuCCRA4-BB: A Fine-Grained Body Biasing Capable DRP Johannes Maximilian Kuhn (Eberhard Karls Universitat Tubingen/Keio University), Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano (Keio University), Oliver Bringmann, and Wolfgang Rosenstiel (Eberhard Karls Universitat Tubingen) |
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| A 20uA/MHz at 200MHz Microcontroller with Low Power Memory Access Scheme for Small Sensing Nodes Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, and Tadaaki Yamauchi (Renesas Electronics Corporation) |
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| ASIC Design of MUL-RED Radix-2 Pipeline FFT Circuit for 802.11ah System Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, and Yasuhiko Nakashima (Nara Institute of Science and Technology) |
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| 12:45-13:55 | Lunch Time Break |
| 13:55-14:35 | Session XII: Invited Presentation 1 Co-chairs: Y. Sato (Tokyo Tech), Y. Kobayashi (NEC) |
| NanoBridge-based FPGA in Harsh Environments Makoto Miyamura (NEC, Japan)(Abstract, Bio) |
|
| 14:35-14:45 | Break |
| 14:45-15:50 | Session XIII: FPGA and Software Co-chairs: Y. Wada (Meisei Univ.), H. Takizawa (Tohoku Univ.) |
| How SIMD Width Affects Energy Efficiency: A Case Study on Sorting Hiroshi Inoue (IBM Research – Tokyo) |
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| Thermal safety through limp home mode for intelligent rear view camera systems Piyali Goswami, Yogesh Marathe, and Kedar Chitnis (Texas Instruments India (Pvt.) Ltd.) |
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| A Power-efficient FPGA Accelerator: Systolic Array with cache-coherent interface for Pair-HMM Algorithm Megumi Ito, and Moriyoshi Ohara (IBM Research – Tokyo) |
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| 15:50-16:10 | Break |
| 16:10-17:00 | Session XIV: Keynote Presentation 5 Co-chairs: R. Egawa (Tohoku Univ.), K. Nitta (NTT Electronics) |
| Cool Techniques for Hot Chips Mateo Valero (Barcelona Supercomputing Center, Spain) (Abstract, Bio) |
|
| 17:00-17:20 | Poster Award and Closing Remarks |