Yokohama Joho Bunka Center (Yokohama Media & Communications Center),
Yokohama, Japan
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The Truths and Myths of Embedded Computing

Shekhar Borkar (Intel, USA)

Abstract: Embedded computing is truly ubiquitous, from household gadgets, hand-held information appliances, computer clients, to the most the powerful mission critical applications. This talk will examine some of the common misconceptions around embedded computing to uncover the truths. We will examine energy efficiency of circuits, heterogeneity in microarchitecture, network on a chip to support communication, memory subsystem to feed the data, fine grain power & energy management, and resiliency. The talk will conclude by painting the vision of even brighter future for embedded computing than what you would have imagined.

Shekhar Borkar graduated with M.Sc in Physics from University of Bombay in 1979, MSEE from University of Notre Dame in 1981 and joined Intel Corp, where he worked on the 8051 family of microcontrollers, and Intel's supercomputers. His research interests are low power, high performance digital circuits, and high speed signaling. Shekhar is an Intel Fellow, an IEEE Fellow, and Director of Exascale Technologies in Intel Labs.

Entering the Era of Crossover SoCs

Patrick Lysaght (Xilinx, USA)

Abstract: Global consumer markets continue to drive the need for ubiquitous computing and an insatiable thirst for communications bandwidth, which are fueling the growth of the electronics industry. Yet the cost of building custom SoCs to support many of the emerging applications is becoming increasingly difficult to justify - except for the highest volume devices. FPGAs provide an attractive alternative today since they eliminate much of the NRE cost and offer tremendous flexibility to adapt to global markets; but density, power and unit cost restrictions have limited the applicability of FPGAs to infrastructure and other relatively low volume applications. Rising to this challenge a new class of "crossover SoCs" is emerging that combines many of the strengths of custom SoCs and FPGAs in a single device. In this session we will discuss the different approaches underway in the industry, including embedded processing subsystems such as the latest ZYNQ architecture announced by Xilinx, 3D interconnect technology, SiP and how they will reshape the device landscape over the next decade.

Patrick Lysaght is a Senior Director in the office of the CTO, in Xilinx San Jose, Ca. He leads a group whose research interests include power estimation, system-level modeling and performance analysis, reconfigurable computing (especially dynamically reconfigurable systems) and emerging design technologies for FPGAs. He also directs the worldwide operation of the Xilinx University Program (XUP). Before joining Xilinx, he held positions as a senior lecturer at the University of Strathclyde (Glasgow) and at the Institute for System Level Integration (Livingston, Scotland). He started his career in research and development with Hewlett Packard (Edinburgh) before going on to hold a number of technical and marketing positions Patrick has co-authored more than fifty technical papers, co-edited two books on programmable logic and holds seven US patents. He is actively involved in the organization of a number of international conferences and is chairman of the steering committee for FPL, the world's largest conference dedicated to field programmable logic. Patrick holds a BSc (Electronic Systems) from the University of Limerick, Ireland and a MSc degree (Digital Techniques) from Heriot-Watt University in Edinburgh, Scotland.

AMD's Zacate, Low Power Fusion APU

Denis Foley (Advanced Micro Devices, USA)

Abstract: AMD's first Fusion APU combines a pair of AMD's newest low-power Bobcat cores with a discrete class GPU on a single 40nm CMOS Bulk Die. There are two versions of the chip  the 18W TDP Zacate and the 9W TDP Ontario. Denis will share details of the Fusion design, implementation and performance highlighting the power savings features of the design.

Denis Foley is a Senior Fellow at Advanced Micro Devices. He has over 27 years experience in the computing industry. At Digital Equipment and Compaq he was a design lead in the Alpha Server group. At Hewlett Packard he was the implementation lead for a high-end Itanium Server. At ATI he was the chip lead for a game console cost-down before turning his attention to low-power design - first as the system architect for a licensable 3D GPU core, then as the system architect for ATI’s Imageon family of application processors for handheld devices. With the AMD acquisition of ATI, Denis moved into the SOC Architect role for a number of AMD’s low-power designs including the recently announced Zacate and Ontario Fusion APUs. Denis is a 1983 graduate of University College Cork, Ireland with a B.Eng(Elect).

Worldwide RMC Mobile Platform Solution

Juha M. Heikkilä (Renesas Mobile Corp., Finland)

Abstract:Renesas Mobile Corporation (RMC), established on the first of December 2010, comes to the global chipset market with advanced and innovative products and services for mobile phones, car infotainment solutions, consumer electronics and industrial applications. The modem group in RMC comes with a strong pedigree from Nokia. The group has developed all Nokia’s in-house modems and formed an essential part of the chipset development for Nokia products since the time of NMT and the first generation of GSM. The world-class and leading wireless connectivity expertise is visible today as widely accepted modem technology and IP in billions of handsets. Renesas Mobile continues on this path by combining the modem asset with Renesas’s unique experience in the field of applications processors, microprocessors and controllers to form a base for highly integrated single- or multichip mobile platforms. This presentation introduces RMC's leading edge technology of GSM, LTE and WCDMA, and also application processors and low power techniques and multi-media performances.

Juha M Heikkilä is VP of ModemSOC in Renesas Mobile Corporation (RMC). RMC is a spin-off and subsidiary of Renesas Electronics Ltd. Juha received his MS degree from the University of Oulu in Finland in Electrical Engineering in 1990. He has over 20 years experience in semiconductor technology and is based in Oulu, Finland. Prior working at Renesas Mobile Corporation, Juha worked 16 years for Nokia in Finland and US. During Nokia years he has been involved with Nokia Baseband ASIC designs in various system engineering, program and organization management positions. Projects he has been involved in include mixed signal and digital baseband ASICs for US-TDMA, GSM, US-CDMA and WCDMA systems as well as number of various phone product programs. The most recent position at Nokia was director of ModemIP in Nokia Wireless Modems. Before Nokia years, Juha was employed five years by independent semiconductor ASIC design house in Finland.

From Multi-Core CPU to Many-Core GPU

Toru Baji (NVIDIA Japan), and Bill Dally (NVIDIA, USA)

Abstract: GPU today is a many-core general-purpose processor. The maximum number of cores supported by the latest Fermi architecture is 512. NVIDIA has introduced CUDA (Compute Unified Device Architecture), a GPU architecture and programming system that abstracts the parallel programming and exploits the efficient usage of many-core GPU. There are more than 200 Million CUDA capable GPUs in the world, more than 100 thousand active GPU computing developers and 362 Universities teaching CUDA Worldwide. Among the top500 supercomputers, the 1st, 3rd and 4th place ones are using CUDA. In this talk, the evolution from CPU to GPU computing architecture will be described. Detail architectures of the 1st generation GPGPU Tesla and 2nd generation GPGPU Fermi will be introduced. Also some insight for the power efficiency of multi-core CPU and many-core GPU will be introduced as a duty in this “Cool Chips” conference. Presentation will be closed with the remark that the targets of the future GPU and CPU roadmaps are also power efficiency.

Toru Baji received his B.S. and M.S. degrees in electronic engineering from Osaka University, Osaka, Japan in 1975 and 1977, respectively. In 1977 he joined Hitachi Central Research Laboratory. From 1984 he stayed at the University of California, Berkeley as a visiting industrial fellow. Back in Hitachi, he worked for high-speed DSP. From 1989 to 1993, he led the design of a RISC type unified DSP architecture in Hitachi America R&D. Back in Japan, he applied this technology to the integration of CPU and DSP, and lead the development of the worldwide 1st CPU-DSP integrated product SH-DSP. From 2001 he served as a technical marketing director of SuperH, Inc., a CPU core IP licensing company at USA. Back in Japan from 2005, he served as a department manager of the automotive application department. In 2008, he joined NVIDIA as a senior solution architect. He is covering a wide range of technology from Tegra mobile processor to GPU computing. He is a member of the IEEE Computer Society.

Invited Presentations

The Correspondence between Architecture and Application for
High Speed Vision Chips

Masatoshi Ishikawa (Tokyo Univ., Japan)

Abstract: High speed vision and its applications of various fields such as robotics, microbiology and user interaction will be shown from the viewpoint of the correspondence between architecture and application. By co-developing application systems and processing architectures of VLSI accordingly, new era of high performance systems will be opened. The architecture of high speed vision is based on fully parallel processing integrated with CMOS photo-detecting circuits and A/D conversion. Massively parallel processing circuits used in the architecture can be integrated into one chip in a high scalable manner. The architecture can realize high-speed image processing with 1 kHz frame rate and above. It makes possible a new style of dynamic image processing as well as novel applications. In this talk, not only basic design concept for application systems and VLSI high speed vision systems, but also various application systems; a high speed batting and throwing robot a visually controlled high-speed dexterous hand, micro-visual feedback microscopy, and 3D tracking systems for capturing human motion and scanning pages of flipped books will be shown by using VIDEOs.

Masatoshi ISHIKAWA received the B.E., M.E. and Dr. Eng. degrees in mathematical engineering and information physics in 1977, 1979 and 1988, respectively, from the University of Tokyo, Japan. From 1979 to 1989, he was a senior researcher at the Ministry of International Trade and Industry’s Industrial Products Research Institute, located at Tsukuba, Japan. Afterwards he was appointed associate professor at the University of Tokyo from 1989 to 1999. From 1999, he was appointed professor of mathematical engineering and information physics at University of Tokyo. From 2001, he has also served as a professor of creative informatics at University of Tokyo. Professor Ishikawa was the vice-president of the University of Tokyo from 2004 to 2005 and also the executive vice-president of University of Tokyo from 2005 to 2006. His current research interests include a VLSI vision chip and its applications, high speed image processing, visual feedback, sensor data fusion, meta-perception, sensor networks, and robotics.

Toward machine vision technology overcoming the pixel resolution limit
--- From 3D vision to medical imaging ---

Takafumi Aoki (Tohoku Univ., Japan)

Abstract: Recently, image matching/correspondence techniques achieving sub-pixel accuracy and higher robustness against image noise have attracted significant attention in real-world visual computing applications. This presentation provides a brief overview of advanced machine vision technology using Phase-Only Correlation (POC) --- an efficient sub-pixel image matching/correspondence technique using phase components in 2D Discrete Fourier Transforms (DFTs) of given images. Since 1990s, our group has carried out systematic research and development of POC-based machine vision algorithms for various applications, where the term "machine vision" is used in a wider sense. Examples of such applications include: (i) biometrics authentication using fingerprints, palmprints, iris, face, dental radiographs, medical volume data, etc., (ii) industrial machine vision for product assembly and inspection, (iii) microscope image analysis for autofocusing and magnification correction, and (iv) video signal processing for video editing, super resolution, video surveillance, etc., (v) 3D measurement and 3D reconstruction of objects with multi-camera images, (vi) vision-based driver-assistance to improve road safety, (vii) robot vision for industrial inspection and human body measurement, (viii) computational photography for high-quality color reproduction, high-resolution image creation, etc., (ix) projector-camera systems for 3D scanning, flexible display walls, AR interaction, artistic creations, etc., and (x) medical image analysis with plain x-ray images, CT/MRI volumes, ultrasonic images, etc. Also, discussed in this presentation are implementation issues of POC-based machine vision algorithms, assuming the use of state-of-the-art GPU technology, as well as DSPs and ASICs.

Takafumi Aoki received the BE, ME, and DE degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1988, 1990, and 1992, respectively. He is currently a professor in the Graduate School of Information Sciences (GSIS) at Tohoku University. Since 2006, Aoki has been appointed as the Special Advisor to the President of Tohoku University. His research interests include theoretical aspects of computation, system LSI design, multiple-valued logic, digital signal processing, image sensing, computer vision, biometric authentication, medical imaging and secure embedded systems. He received more than 20 academic awards, including the IEE Ambrose Fleming Premium Award (1994), the IEE Mountbatten Premium Award (1999), the IEICE Outstanding Transaction Paper Awards (1989 and 1997), the IEICE Inose Award (1997), the Ichimura Award (2008), as well as many outstanding paper awards from international conferences such as ISMVL, ISPACS and SASIMI.

Full Software Implementation of Real-time ISDB-T Modulator on Dynamically Reconfigurable SoC Using Practical Co-design Environment

Toru Awashima (Renesas Electronics, Japan)

Abstract: Overview of our original dynamically reconfigurable SoC and case study of its application development are presented. The experienced results demonstrate efficiency of our design platform. Essential key technologies are dynamically reconfigurable processor: DRP, C language based integrated design environment, and practical support for software hardware co-design. DRP is a coarse grained multi context type reconfigurable architecture. Since data paths can be reconfigured within 1ns, this architecture is area efficient thus suitable for embedded core for SoC. XBridge® is one commercial ASSP which has DRP (with intelligent DMA I/F) as an on-chip accelerator. We developed a sophisticated integrated design environment based on C language based behavioral synthesizer. Algorithm designer can directly design DRP application using conventional C language. As a case study, development of Digital TV application: real-time ISDB-T modulator is presented. At the first stage the application is written in pure C description to be run on the CPU. After that the designer tries to optimize the overall performance by offloading crucial part to DRP. C based practical co-design environment continuously support the optimizing process. The keywords are portability, scalability, and transparency, all come from All-in-C concept.

Toru Awashima is a development manager of SoC business unit of Renesas Electronics. His recent work related to dynamically reconfigurable architecture, its design flow, applications, and business model development. He received his BS, MS, Dr. of Engineering degree from Waseda University, Tokyo Japan, in 1988, 1990, and 1993 respectively. From 1993 to 2010 he has been a researcher at Central Research Laboratories of NEC Corporation. His research topics were physical design automation and reconfigurable architecture. His interest is not only in technology side, but also in new business model and marketing. So he received his MBA degree from Aoyama Gakuin University in 2010. Then he joined Renesas Electronics (joint company of NEC Electronics and Renesas Technology) for development of reconfigurable device technology and its business model. He is a member of IEEE.

Panel Discussion

Topics: Impact on society by fusion and harmony of mobile devices, servers, and networks
-- Their direction of evolutions and optimal roles --

Organizer & Modelator: Masato Motomura (Hokkaido Univ.)

Abstract: It is now clear that variety of mobile devices around us, such as smartphones and smart-tablets, have started to change our everyday lives. Further, camera or sensor equipped devices will be popular to realize more sophisticated appliances or social environments. Needless to say, such devices are connected to servers in datacenters through networks. A given processing task may either be handled in the devices or servers, or both, where optimal system balance being dependent on application characteristics (such as required response time, data aggregation scheme, etc.) and performance/bandwidth distribution in such total systems. In this panel, experienced panelists will disclose their perspective on potential applications that may prevail in near future. Based on that, they will discuss promising technology direction, that may largely affect optimal system balance mentioned above.

Masato Motomura received his BS and MS degrees in physics and Ph.D degree in electrical engineering in 1985, 1987, and 1996, all from Kyoto University. He had been with NEC and NEC Electronics from 1987 to 2011, and has moved to Hokkaido University this month. His research interests include reconfigurable and parallel architectures and low power circuits. He has won the JSSC Annual Best Paper Award in 1992, and the IPSJ Annual Best Paper Award in 1999. He is a member of IEICE and IEEE.

Special Sessions (invited lectures)

Trusted MpSoC platforms for safety related applications

Rolf Ernst (Technische Universitat Braunschweig, Germany)

Abstract: MpSoCs are efficient platforms for systems integration. However, due to physical resource sharing, safety critical systems integration becomes more challenging compared to distributed systems potentially leading to increasing design and certification cost. There are many issues in efficient error detection and handling, function segregation, timing, or in the RTE interface that require system level hardware/software solutions. Integration frequently leads to mixed critical systems, i.e. systems which combine functions of different criticality levels. One of the main requirements is a flexible trade-off between development, certification, and production cost that is highly influenced by production volume, product lifetime, and system criticality. The talk will introduce to the design of safety critical systems, and the derived design challenges for MpSoC based systems. Novel solutions and tool technologies will be explained. The talk will also give an overview on several large industrial-academic projects that deal with safety critical MpSoC and their application, such as the ARTEMIS RECOMP project (Reduced Certification Costs for Trusted Multi-core Platforms).

Rolf Ernst received a diploma in CS and a Dr.-Ing. in EE from the University of Erlangen-Nuremberg, Germany, in 81 and 87. From 88 to 89, he was with Bell Laboratories, Allentown, USA. Since 90, he has been a professor of electrical engineering at the Technische Universitat Braunschweig, Germany, where he chairs a university institute of 65 researchers and staff. His research activities include embedded system design and design automation. The activities are currently supported by the German "Deutsche Forschungsgemeinschaft" (corresponds to the NSF), by the German BMBF, by the European Union, and by industrial contracts, such as from Intel, Daimler, GM, or Volkswagen. He gave numerous invited presentations and tutorials at major international events and contributed to seminars and summer schools in the areas of hardware/software co-design, embedded system architectures, system modeling and verification. His spin-off, Symtavision, provides system level analysis and optimization solutions to companies worldwide. He chaired major events, such as ICCAD or DATE. He is a member of the European ARTEMIS strategic research agenda team and served as an expert for the respective German embedded systems roadmap. He is an IEEE Fellow and served as an ACM-SIGDA Distinguished Lecturer. He is a member of the German Academy of Science and Engineering, acatech.

Power Measurement, Characterization and Estimation of Microprocessor-Based Systems

Naehyuck Chang (Seoul National University, Korea)

Abstract: Modern microprocessor systems are equipped with various types of memory and peripheral devices/subsystems. Power consumption of such devices and subsystems are complicated due to advanced access protocols and levels of power modes. Most of all, their power consumption is primarily dependent on the system behavior, which is again determined by the program and runtime data running on the microprocessor. Accurate power measurement, characterization and estimation of such systems are expensive, but we should not compromise accuracy with cost. In this talk, we present a systematic approach aiming at high-fidelity and cost-effective power measurement, characterization and estimation methods introducing cycle-accurate energy measurement tools, an energy state machine which can separately annotate dynamic and leakage power, and cycle-accurate system-level power simulation, followed by on-line power estimation using an on-chip bus performance monitoring unit. High-fidelity power measurement, characterization and estimation provide unique high-level power behavioral information that inspires innovative low-power design techniques. We also introduce several case studies of high-level power management techniques, which are motivated from the unique power characteristics of memory and peripheral devices and subsystems.

Naehyuck Chang is a Full Professor in Dept. of Electrical Engineering and Computer Science, Seoul National University, Korea. He was a Visiting Associate Professor at Arizona State University in 2005, and a Visiting Professor at University of Southern California in 2009-2010. He serves (and served) as Technical Program Committee of ACM SIGDA, IEEE CASS and other related conferences and symposiums such as DAC, ICCAD, ISLPED, DATE, ASP-DAC, GLS-VLSI, ISQED, PATMOS, ESTIMedia, ICCD, and so on. He also serves as Committee Member of ACM SIGDA PhD Forum, ACM/IEEE ASP-DAC Student Forum, and SIGDA Graduate Scholarship. He served as the Technical Program Co-Chair of RTCSA in 2007, ISLPED in 2009, and ESTIMedia in 2009 and 2010. He is General-Vice Chair of ISLPED 2010, and General Co-Chair of ISLPED 2011. He served as an organizing committee member of AP-ASIC 2004 (Registration Chair), ESWeek 2006 (Local arrangement and registration Chair), ASP-DAC 2008 (Student Forum Chair). He is General Vice-Chair of ISLPED 2010, and will be a General Chair of ISLPED 2011. He is an Associate Editor of IEEE TCAD and ACM TODAES, and editorial board members of JOLPE and JEC. He is a guest editor of ACM TODAES and TECS for low-power design and embedded multi-media systems, respectively, in 2010. He also serves as the Chair of ACM SIGDA Low-Power Technical Committee, ASP-DAC SIGDA Representative and ACM SIGDA Executive Committee (Technical Activity Chair). He is a Senior Member of ACM and IEEE.